1. Field of the Invention
The present invention generally relates to the fabrication of modular electronic circuit packages and, more particularly, to electronic circuit packages having multi-layer electrical interconnection patterns and which are capable of providing signal and power connections to one or more integrated circuit chips and/or interconnecting a plurality of integrated circuit chips.
2. Description of the Prior Art
The trend toward fabrication of electronic circuit devices at smaller sizes and higher integration densities is principally due to the higher circuit performance which is generally associated with reduced size and interconnection distances. Reduction in size of electronic circuits is often accompanied by reduced parasitic capacitances, shortened signal propagation times and reduced power dissipation. Additionally, the process cost is generally reduced with the size of a circuit of a given design complexity since such size reduction allows more such circuits to be formed on a single semiconductor wafer of a given size or through the use of equipment of a fixed processing capacity. Therefore process costs can be projected over a larger number of devices even though some process complexities and costs may be increased as feature sizes in the integrated circuit design approach the limits reliably available at any given time.
To fully exploit the performance improvements available from reduced propagation time as well as reduced costs deriving from increased integration density, chip interconnection systems must be able to mechanically support a potentially large plurality of integrated circuit chips in close proximity and provide potentially complex electrical interconnection thereof at relatively low cost and with high reliability. Such interconnection systems often cannot be provided as an incident of circuit integration on a single chip since incompatible processes are often required to form optimal integrated circuits having different functions. Accordingly, to meet the need for interconnection of a potentially large plurality of integrated circuit chips, so-called multi-layer modules (MLM's) have been developed which include a plurality of lamina having desired circuit interconnection patterns formed thereon. These lamina, which may be of a variety of materials such as ceramic or polymers (e.g. polyimide) are then stacked and formed into a single body by heat treatment such as sintering for ceramics or fusing for polymers.
Connections between conductive patterns formed on respective lamina of MLM's is achieved by the formation of vias (e.g. generally by punching or drilling) which are essentially perforations in the respective lamina which are later filled with a conductive material such as metal or a conductive paste such as that used to form the conductive patterns. Often, conductive spheres or cylinders will be embedded into the lamina to form vias with a reduced number of process steps. Preferred methods of via formation are not consistent for all materials of which the lamina may be made; requiring different machinery and process steps for different lamina and via materials.
The completion of vias in each lamina before the lamina are joined together, however, implies a requirement that the process for joining the lamina must also form good electrical connections at the via locations in one lamina to the conductive pattern on an adjacent lamina. This process, though presently well-developed and highly reliable generally causes residual stress in the lamina and the completed MLM. Additional stresses may occur during lamination or curing of the lamina, as well, with the result that there will generally be some dimensional distortion of the lamina during the process which may compromise alignment. Such stress is partially borne by the via connections and may be relieved during thermal cycling or other mechanisms after the MLM is placed in service with the result that via connections may become less reliable as stress is relieved.
Further, process tolerance for forming the via connections within the body of the MLM is relatively critical and inherently does not result in a structure of optimal robustness. It should also be recognized that the number of vias in each lamina may be in the thousands and the number of connections which are simultaneously formed is therefore many times larger and will increase as the number of lamina and or the number of vias per lamina required by the MLM design increases. Therefore, the possibility of the improper or less than ideal formation of one or more connections in the MLM greatly increases and robustness is compromised with increased complexity of the MLM design.
Additionally, it should be recognized that the process for forming MLM's in this way is expensive and complex; requiring numerous steps to be carried out with high precision, particularly as to positional registration as the lamina are stacked. Automated optical alignment cannot generally be accomplished without the formation of a plurality of transparent features or apertures which would occupy module space and further complicate manufacturing processes. Further, the formation of vias by punching or drilling carries the possibility of contamination of the lamina with the material removed from the vias. Punching and drilling processes usually must be performed serially (e.g. one via after another) and, even when carried out at high speed, the number of vias inherently extends the time required for the formation of vias in each lamina.
Sequential drilling and punching also allows the possibility of individual, relative, positional errors and via malformations such as may occur through so-called "wandering" of a drill bit as a hole is begun or through mechanical recoil or bounce of a punch. Correct formation of the via apertures and the filling thereof must also be verified by serial inspection or testing (e.g. optical inspection) of each via before and after filling. Therefore, punching and drilling processes and the inspection or testing processes required for verification of via formation and filling are inherently expensive since costly, high-precision machines are required for an extended period of time for each lamina and the cost of such machinery and its maintenance must be amortized over the number of devices produced, increasing the production cost of such devices.
Also, since the lamina are worked individually, while vias are formed, the potential for variation from uniformity is substantial and substantially exact repeatability is not assured. Filling of the vias is also difficult and less than fully reliable; often requiring inspection of each via in each lamina prior to lamination by stacking and joining.
As an additional complication, the electrical requirements for power and signal connections are very different. Signal connections require very little current to be carried and parasitic capacitances are relatively critical to the propagation of signals having significant voltage swings. Power connections, however, must carry substantial current but the current may vary widely while voltage variation must be kept to a minimum. Heat dissipation may also be an important consideration in the design of power connections. For this reason, power and signal connections are generally formed on different lamina of a multi-layer interconnection structure.
However, the use of different layers or lamina for different types of connections necessarily implies that some connections must pass through other layers or lamina by the use of vias. Short signal paths also generally implies that signal connection lamina and power connection lamina should be grouped together toward opposite sides of the multi-layer interconnections structure (i.e. the signal layers grouped near the top where integrated circuits are to be attached and power layers grouped in lower layers. The use of vias for interlayer connections also implies a substantial uniformity of conductor structures which must be used to meet the differing requirements of power and signal connections which are usually optimized in design for signals and a large plurality of vias used for power connections. For example, it is not unusual for 25% or more of the connections to integrated circuit chips to be dedicated to power connections and a similar fraction of available vias may be used for power connections in interconnection modules, as well. In fact, a higher percentage of vias may be required because of the relatively greater length of power connections through vias when power connection layers are grouped in the lower layers of a module. The number of power connections may also restrict design flexibility in regard to the number and location of vias available for signal connections. Due to the possibility of ohmic heating of power connections, circuitous connections through the MLM are undesirable and vias used for power connections are often formed by a group of adjacent vias of significant extent.
In practical effect, the combination of problems encountered in known multi-layer interconnection structures requires that wiring density be limited to a lower density than that which can be achieved at the present state of the art. For example, vias must be made larger and spacing between conductors must be increased to accommodate slight misregistration between lamina in order to achieve acceptable manufacturing yields. This limitation on wiring density also limits reduction of size and, hence, some performance parameters of electronic modules as well as limiting the economy with which such modules may be produced.